1. Field of the Invention
The present invention relates to a decoding apparatus and a decoding method of a mobile communication system. More particularly, the present invention relates to a turbo decoder and a decoding method, which use a Maximum A Posteriori (MAP) algorithm in order to perform iterative decoding.
2. Description of the Related Art
In general, in order to correct an error of a channel transmitted through wireless environments, a wireless mobile communication system uses a channel estimation method by which a transmitter performs a coding operation using an error correction code and a receiver corrects the error for the received channel.
A correctable coding scheme for performing such an error correction includes a method using a convolutional code and a method using a turbo code. In the embodiments of the present invention, a method for correcting an error using a turbo code will be described. The conventional turbo code is employed when channels of a high data rate are coded or decoded in a CDMA 2000 used in USA and a W-CDMA used in Europe. This turbo code is subjected to iterative decoding even in low reception power, so that the turbo code has a value approximate to the Shannon Limit, which is a theoretical limit. In particular, the turbo code is usually used when a high speed image signal service and a data service are provided.
A decoding method of the conventional turbo code includes a Soft-Output Viterbi Algorithm (SOVA) scheme and an MAP scheme. A receiver performs iterative decoding operation by means of the decoding schemes and thus restores the original information transmitted from a transmitter. In general, when a decoding operation is performed by means of the SOVA, a decoder separately requires predetermined bits in consideration of a dynamic range increased by the Branch Metric Calculation (BMC).
Further, when a decoding operation is performed by means of the MAP, a decoder further requires predetermined bits because the internal BMC is determined by a code rate. However, a decoder using the SOVA has a reduced Bit Error Rate (BER) performance as compared with a decoder using the MAP.
For example, as compared with the SOVA scheme, an MAP scheme has a higher coding gain by about 0.3 dB in Additive White Gaussian Noise environments having good channel conditions and by about 3 dB in Rayleigh Fading environments having bad channel conditions.
FIG. 1 is a block diagram schematically showing the structure of a general turbo decoder.
Referring to FIG. 1, the conventional turbo decoder of a transmitter divides the data to be transmitted into a systematic bit X, a first parity bit y1 and a second parity bit y2 and outputs the systematic bit X, the first parity bit y1 and the second parity bit y2. Then, a turbo decoder of a receiver receives the systematic bit X, the first parity bit y1 and the second parity bit y2 and decodes the received bits by means of two decoders 120 and 150, an interleaver 140 and a deinterleaver 170. First, the first decoder 120 decodes the forward input data x and y1 and the second decoder 150 decodes the randomly input data x and y1. The forward input data x is summed with the output from the deinterleaver 170 by adder 110. Accordingly, the interleaver 140 is disposed before the second decoder 150 and interleaves the input data x, which is again summed with the output of deinterleaver 170 by adder 130 and y1. Then, the second decoder 150 decodes the interleaved data. The first decoder 120 and the second decoder 150 inputs a soft signal value of a bit group including plural bits, which is similar to a frame, and outputs a decoded soft signal value. Further, the deinterleaver 170 aligns the data, which have been interleaved by the interleaver 140, according to an input sequence, which is the sum of the output from the second decoder 150 and the interleaver 140, from adder 160. Herein, the decoder may be used as a Recursive Systematic Convolutional (RSC) encoder. In relation to the decoders 120 and 150 of FIG. 1, a decoder using an MAP scheme is shown in FIG. 2.
FIG. 2 is a block diagram schematically showing the structure of a conventional decoder using the MAP scheme.
Referring to FIG. 2, an alpha shift buffer 210 receives data input by the frame unit and transfers the received data to an alpha metric block 214 through a first delta block 212. Herein, the alpha shift buffer 210 transfers the input data so that the data is calculated in the forward direction. The alpha metric block 214 performs a calculation for the forward input data of four windows each time.
Further, a beta 1 shift buffer 220 outputs data corresponding to the size of two windows in accordance with the output having a four window size of the alpha shift buffer 210. Herein, the data output through the beta 1 shift buffer 220 is transmitted to a beta 1 metric block 224 through a second delta block 222. The beta 1 metric block 224 performs a backward metric calculation for the input data and the calculated data is stored in a beta 1 buffer 226.
Further, a beta 2 shift buffer 230 outputs data corresponding to the size of two windows. Herein, in contrast with the beta 1 shift buffer 220, the beta 2 shift buffer 230 delays data of one window size and outputs undelayed data. The data output through the beta 2 shift buffer 230 is transmitted to a beta 2 metric block 234 through a third delta block 232. Herein, the beta 2 metric block 234 delays information of the first input window and performs a backward metric calculation for the input data. Further, the calculated data is stored in a beta 2 buffer 236.
A multiplexer 240 receives the beta metric calculation values output through the beta 1 metric block 224 from the beta 1 buffer 226 and the beta 2 metric block 234 from the beta 2 buffer 236, and selectively outputs only valid values. That is, the multiplexer 240 selects a block, which actually outputs valid beta metric calculation values, and transmits data to a Log-Likelihood Ratio (LLR) generation circuit 250. The LLR generation circuit 250 receives output values corresponding to four window sizes output through the alpha shift buffer 210 and the valid beta metric calculation values, and restores the originally transmitted data.
FIG. 3 is a diagram illustrating the operations of buffers corresponding to input data in a decoder using a conventional MAP scheme.
Referring to FIG. 3, the decoder uses plural buffers (such as memories) for storing the input data according to window size W blocks and constructs a system. First, since the decoder performs an alpha metric calculation, it requires four memories corresponding to window size W. Further, since the decoder performs a beta metric calculation, it requires two memories corresponding to window size W. That is, in order to perform one decoding operation, the decoder requires at least eight memories corresponding to window size W. Therefore, design of the memory may result in inefficiencies of design.
In relation to the buffers of FIG. 3, a process for calculating an LLR by performing a metric calculation for the data output from each buffer will be described with reference to FIG. 4.
FIG. 4 is a diagram illustrating a conventional process for processing data according to a BMC for input data.
Referring to FIG. 4, the codewords of eight bits output from the alpha shift buffer 210 are output to the alpha metric block 214 through the first delta block 212. Herein, since the alpha metric block 214 uses a buffer having four window size W blocks, the alpha metric 214 sequentially outputs codeword data of four bits. For example, data (0, 1, 2, 3) and (4, 5, 6, 7) is sequentially input to the alpha shift buffer 210 (400). The input data is sequentially output by the four windows (0, 1, 2, 3) of the data through a calculation process in the alpha metric block 214 (401).
Herein, when a path metric of two bits is performed by the first delta block 212, the beta 1 shift buffer 220 outputs stored data in accordance with the operation of the alpha shift buffer 210 of eight bits. That is, the beta 1 metric block 224 starts to receive data of two window size W blocks in the backward direction in accordance with four memories for metric states of eight bits output from the alpha shift buffer 210. Herein, when data is stored in the alpha metric block 214 by the size of two buffers, the first data of the beta 1 shift buffer 220 is output. The beta 1 metric block 224 receives the data in a backward direction.
For example, the beta 1 shift buffer 220 outputs (421) data of two window size in the backward direction in accordance with (400) the sequentially input data. That is, the input data (0, 1, 2, 3) and (4, 5, 6, 7) is input in a sequence of (1, 0), (3, 2) and (5, 4) through a calculation process in the beta 1 metric block 224 (421). Herein, the beta 1 metric block 224 outputs valid values 0 and 2 of the calculated values to the beta 1 buffer 226 (422).
Further, the beta 2 metric block 234 delays the first window of the input data and outputs data of two window size in the backward direction. That is, the beta 2 metric block 234 delays the first data in accordance with four memories for metric states of eight bits output from the alpha shift buffer 210, and then starts to receive data of two window size W blocks in a backward direction.
For example, the beta 2 shift buffer 230 delays data of one window size in accordance with the sequentially input data (440) and then outputs undelayed data of two window size in the backward direction (441). That is, the input data (1, 2, 3) and (4, 5, 6, 7) is input in a sequence of (2, 1) and (4, 3) and 6 through a calculation process in the beta 2 metric block 234 (441). Herein, the beta 2 metric block 234 outputs valid values 1 and 3 of the calculated values to the beta 2 buffer 236 (442).
The valid values stored in the beta 1 buffer 226 and the beta 2 buffer 236 are selectively output to the LLR generation circuit 250 by the multiplexer 240 in accordance with a value output from the alpha metric block 214.
This results from the MAP coding process of the turbo code. That is, the channel input of the decoder and an LLR value output from another decoder are input and subjected to the BMC and an Add-Compare Select (ACS), thereby generating an LLR value.
As described above, a forward metric calculation and a backward metric calculation are performed in order to perform the MAP algorithm. Further, the alpha metric calculation is performed in the forward direction and the beta metric calculation is performed in the backward direction under the alpha metric calculation.
Such a decoding process is repeated so as to generate an LLR value having high reliability and iterative decoding is performed by a maximum iteration value, so that a Cyclic Redundancy Check (CRC) is performed. Therefore, a hard decision is finally obtained.
However, the MAP decoding process as described above has the following problems.
First, since the backward metric calculation is performed, additional memories are necessary for storing the input data. The memory includes the beta 1 shift buffer 220 and the beta 2 shift buffer 230 according to the backward metric calculation. Herein, it is necessary to provide each calculation block with separate control logics for controlling the memories, that is, the alpha shift buffer 210, the beta 1 shift buffer 220 and the beta 2 shift buffer 230.
Second, the backward metric calculation starts at the last portion of a frame and is updated at each trellis transition. That is, the backward metric calculation always experiences an update process. Therefore, delays occur due to the data update.